Delay locked loops (DLLs) are often used in integrated circuits (ICs) to generate an internal clock signal. In a typical DLL, the internal clock signal is generated by a digital controlled delay line (DCDL). The DCDL is used to prevent an external clock signal from arriving at an output until a predetermined time has elapsed. The DCDL typically contains several delay cells, with each of the delay cells having a corresponding delay time. Total delay time in the DCDL is determined by increasing or decreasing the number of delay cells that a signal passes through. To achieve finer granularity in delay time adjustments, the DCDL includes a huge amount of delay cells that consume enormous operation power.